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| CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Features * * * * * * * * * * 400-ps max Total Timing Budget (TTB) window 10 LVPECL outputs 1 LVPECL differential input Selectable output frequency range from 100 to 400 MHz Multiply by 2 option 15-ps RMS Cycle-Cycle Jitter Power-down mode Lock indicator 3.3V power supply Available in 48-pin QFN package Overview TheCY23020-3 is a high-performance 400-MHz LVPECL Output phase-locked loop (PLL)-based zero delay buffer (ZDB) designed for high- speed clock distribution applications. The device features a guaranteed TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in voltage, temperature, process, frequency, and ramp rate. Additionally, the CY23020-3 can be used as a fan-out buffer via the S[1:2] control pins. In this mode, the PLL is bypassed and the reference clock is routed to the output buffers. Block Diagram 48 Pin Configurations 47 V D D 46 F B I N + 45 F B I N 44 N C 43 L O C K 42 V D D C 41 G N D C 40 R E F 39 R E F + 38 V D D 37 Q 9 + Q9- 36 GND 35 Q8- 34 Q8+ 33 VDD 32 LOCK FBOUT+ FBOUT- REF+ REFFBIN+ FBIN- /1//2 1 2 3 4 5 6 FBOUTGND Q1Q1+ VDD Q2+ Q2GND Q3Q3+ VDD Q4+ /1 /2 PLL Q1+ Q1Q2+ Q2Q3+ Q3Q4+ Q4- F B O U T + CY23020-3 Q7+ 31 Q7- 30 GND 29 Q6- 28 Q6+ 27 VDD 26 Q5+ 25 S1:2 RANGE MUL Control Logic Q5+ Q4Q6+ Q6Q7+ Q7Q8+ Q8Q9+ Q9- 7 8 9 10 11 12 Q 4 - G N D S 2 S 1 M U L R A N G E 18 G N D C 19 V D D C 20 V D D C 21 G N D C G N D Q 5 - 13 14 15 16 17 22 23 24 Cypress Semiconductor Corporation Document #: 38-07473 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised June 5, 2003 CY23020-3 Pin Definitions[1] Pin Name REF+ REFFBIN+ FBINPin No. 39 40 46 45 Pin Type I Pin Description Reference Inputs. Output signals are synchronized to the crossing point of REF+ and REF- signals. In DC mode, the REF+/REF- inputs must be held at opposite logical states. For optimal performance, the impedances seen by these two inputs must be equal. Feedback Inputs. Input FBIN+/FBIN- must be fed by one of the outputs to ensure proper functionality. If the trace between FBIN+/FBIN- and FBOUT+/FBOUT- is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the clock signal at REF+/REF- inputs. In DC mode, FBIN+/FBIN- inputs must be held at opposite logical states. For best performance, the impedances seen by these two inputs must be equal. Feedback Output. In order to complete the phase locked loop, similar polarity outputs must be connected back to the FBIN+ and FBIN- pins. Any of the outputs may actually be used as the feedback source. Differential Q1 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q2 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q3 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q4 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q5 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q6 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q7 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q8 Outputs. Refer to Tables 1,2, and 3 for configuration. Differential Q9 Outputs. Refer to Tables 1,2, and 3 for configuration. Frequency Range Selection Input. To determine the correct connection for this pin, refer to Table 2. This should be a static input PLL Locked Output. When this output is HIGH, the PLL in the CY23020-3 is in steady state operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto the reference signal. Output/PLL Enable Selection Bits. Refer to Table 1. Analog Power Connection. Connect to 3.3V. Analog Ground Connection. Connect to common system ground plane. Output Buffer Power Connections. Connect 3.3V Ground Connections. Connect to common system ground plane. Multiplication Factor Select. When set HIGH, the outputs will run at twice the speed of the reference signal. This should be a static input. Do Not Connect. This pin must be left floating. This pin is used by the factory for testing purposes. I FBOUT+ FBOUTQ1+, Q1Q2+, Q2Q3+, Q3Q4 +, Q4Q5+, Q5Q6+, Q6Q7+, Q7Q8+, Q8Q9+, Q9RANGE LOCK 1 48 1 4, 3 6, 7 10, 9 12, 13 25, 24 27, 28 31, 30 33, 34 37, 36 18 43 O O O O O O O O O O I O S1:2 VDDC GNDC VDD GND MUL[2] NC 16, 15 20, 21, 42 19, 22, 41 5, 11, 26, 32, 38, 47 2, 8, 14, 23, 29, 35 17 44 I P G P G I NC Table 1. Output Configuration S1 0 0 1 1 S2 0 1 0 1 Three-state Reserved Reference Input PLL Output Shutdown Enabled Outputs PLL Shutdown Notes: 1. There are no power-up sequence requirements on the power supply pins of the CY23020-3. 2. RANGE and MUL have a ~100k pull-down. Document #: 38-07473 Rev. *A Page 2 of 9 CY23020-3 Table 2. Frequency Range Setting RANGE 0 1 Output Frequency Range 100-200 MHz 200-400 MHz Inserting Other Devices in Feedback Path Due to the fact that the device has an external feedback path the user has a wide range of control over its output to input skewing effect. One of these is to be able to synchronize the outputs of an external clock that is resultant from any of the output clocks. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 1, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin (B), the signals at the destination(s) device (C) will be driven high at the same time the Reference clock provided to the ZDB goes high. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. There are constraints when inserting other devices. If the devices contain PLLs or excessively long delay times they can easily cause the overall clocking system to become unstable as the components interact. For these designs it is advisable to contact Cypress for applications support. Reference Signal Feedback Input Table 3. Frequency Multiplication Table MUL 0 1 Output Frequency = REF = 2 * REF How to Implement Zero Delay Typically, ZDBs multiply (fan-out) single-clock signals quantity while simultaneously reducing or mitigating the time delay associated with passing the clock through a buffering device. In many cases the output clock is adjusted, in phase, to occur later or more often before the device's input clock to compensate for a design's physical delay inadequacies. Most commonly this is done using a simple PCB trace as a time delay element. The longer the trace the earlier the output clock edges occur with respect to the reference input clock edges. In this way such effects as undesired transit time of a clock signal across a PCB can be compensated for. C Zero Delay Buffer ASIC/ Buffer A B Table 4. Absolute Maximum Ratings[3] Parameter VDD VIN TSTG TA Description Voltage on any VDD pin with respect to GND Voltage on any input pin with respect to GND Storage Temperature Operation Temperature (QFN) -0.5 to +5.0 -0.5 to VDD + 0.5 -65 to +150 -40 to 85 135 VCC = 3.135 Parameter VOH VOL VOH (rel to VCC) VOL(rel to VCC) These result in the following mid point values:[4] VMID ((VOH + VOL)/2) VMID Relative to VCC 1.485 -1.65 2.085 -1.05 1.65 -1.65 2.25 -1.05 1.815 -1.65 2.415 -1.05 Description Conditions Min. 1.835 1.135 -1.3 -2 Max. 2.435 1.735 -0.7 -1.4 VCC = 3.3 Min. 2 1.3 -1.3 -2 Max. 2.6 1.9 -0.7 -1.4 Figure 1. Output Buffer in Feedback Path Rating Unit V V C C C VCC = 3.465 Min. 2.165 1.465 -1.3 -2 Max. 2.765 2.065 -0.7 -1.4 TJ Junction Temperature Table 5. PECL DC Output Specification [4] Notes: 3. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 4. The midpoint voltage is average value of a waveform. For differential signals the midpoint is assumed to be the same for both the true and complement since the VOH and VOL of both the true and complement signals in general should be the same. VMID is not necessarily equal to the differential crossover voltage, which may be skewed if there is differential time delays between the signals. Document #: 38-07473 Rev. *A Page 3 of 9 CY23020-3 Table 5. PECL DC Output Specification (continued)[4] VCC = 3.135 Parameter IPD IIL IIH Description Power-down Current Conditions 70C, VDDmax VIN = 0 VIN = VDD Min. Min. Max. VCC = 3.3 Min. Max. 100 10 100 Max. VCC = 3.465 Min. Unit A A A Max. Table 6. VDDC = 3.3V 5%, VDD = 3.3V 5% (See Test Set-ups, CL = 5 pF) Parameter IDD CIN CL[5] VISW VIX SI [6] Description Condition Loaded, VDD max, Cold, 400 MHz, all outputs switching Min. Typ. Max. 300 Unit mA pF pF V REF or FBIN Pin Capacitance Load Cap Single Ended Input Swing Input Crossover Voltage (expressed relative to VDD) Input Slew Rate Measured from VIX MEAS + 0.15 to VIX MEAS -0.15. (20- 80% of a min input swing sig.) VOMID = (VH_MEAS VL_MEAS)/2 VOMID = (VH_MEAS VL_MEAS)/2 4 0.5 VDD - 1.79 0.9 5 5 6 1.25 VDD - 0.96 4 V/ns VOSW VOX [7] Single Ended Output Swing Output Crossing Point Output Crossing Point (relative to VDD) 0.6 VOMID - 0.20 VDD - 1.79 1.1 VOMID - 0.20 VDD - 0.96 V VOX[8] Table 7. VDDC = 3.3V 5%, VDD = 3.3V 5% (See Test Set-ups, CL = 5 pF) Parameter SO DI DO TPDIO TPDIOD TPDO TPDOB TPDOB133 TTB TJCCPP TJCCRMS Tjccop Tjrms Total Timing Budget Cycle-Cycle Jitter (1000 cycles) p-p RMS Cycle-Cycle Jitter REF and outputs, same frequency REF and outputs, same frequency Ref = x2 Ref = x2 Description Output Rise/Fall Slew Rate Input Duty Cycle Output Duty Cycle REFin-FBin prop delay REFin-FBin prop delay FBout to any output prop delay Output-Output skew within a bank Output-Output skew @133 MHz 75 400 100 15 125 30 Condition Measured from VIX MEAS + 0.15 to VIX MEAS -0.15. (20-80% of a min input swing sig.) Input duty cycle Differential crossing point External feedback REF, FB same frequency External feedback REF, FB same frequency x2 Min. 0.9 40 45 -50 -50 -325 Typ. Max. 2 60 55 200 150 -100 150 Unit V/ns % % ps ps ps ps ps ps ps ps ps ps Notes: 5. Same as input. PECL is assumed to drive single point loads. 6. This is the output DC mid-voltage range the crossover voltage tolerance. Refer Input Voltage is assumed to be derived from same supply as part. This is why it is spec'd relative to VDD. 7. Crossover is within 20% of the center of the minimum swing. 8. Crossover is within 20% of the center of the minimum swing. Document #: 38-07473 Rev. *A Page 4 of 9 CY23020-3 0.57 ns FBIN+ OUT All board transmission lines 50 and 0.57 ns propagation delay REFIN- OUT 50 FBIN+ = REF- 100 FBIN+ OUT REFIN+ OUT 50 FBIN+ REF+ 2.3ns PULSE GEN C Selected to produce 1-2.5V/ns at pin FBOUT+ Q5+ 100 FBOUT- Q5- Q1+ 100 CL Q1CL Q4+ 100 Q4- Figure 2. Test Set-up 1 Example Document #: 38-07473 Rev. *A Page 5 of 9 CY23020-3 0.57ns FBIN+ OUT 50 450 = REF- All board transmission lines 50 and 0.57ns propagation delay . REFIN- OUT 50 FBIN+ FBIN+ OUT 100 REFIN+ OUT 450 FBIN+ REF+ 50 2.3ns 50 PULSE GEN C Selected to produce 1-2.5V/ns at pin FBOUT+ Q5+ 100 FBOUT- Q5- Q1+ 100 CL Q1CL Q4+ 100 Q4- Figure 3. Test Set-up 2 Example[9] Note: 9. The above configuration may provide better termination at the FBIN input. Document #: 38-07473 Rev. *A Page 6 of 9 CY23020-3 0.57ns FBIN+ OUT All board transmission lines 50 and 0.57ns propagation delay. REFIN - OUT 50 FBIN -+ = REF - 100 FBIN+ OUT REFIN+ OUT 50 FBIN+ REF+ PULSE GEN C Selected to produce 1-2.5V/ns at pin FBOUT+ 100 CL Q5+ 100 FBOUT Q 5- Q1+ 100 CL Q1- Q4+ 100 Q4- Figure 4. Test Set-up 3 Example[10] Ordering Information Ordering Code CY23020LFI-3 CY23020LFI-3T 48-pin QFN 48-pin QFN-Tape and Reel Package Type Temperature Range Industrial, -40C to +85C Industrial, -40C to +85C Note: 10. If accurate pin-pin skew is not obtainable with the load capacitors, a third configuration can be made with no load C. In this case only pin-pin skew is characterized. Part must be in PLL bypass mode. Document #: 38-07473 Rev. *A Page 7 of 9 CY23020-3 Package Drawing and Dimension 48-lead QFN (7 x 7 mm) LF48 51-85152-*A Total Timing Budget and TTB are trademarks of Cypress Semiconductor. All product and company names listed in this document are the trademarks of their respective holders. Document #: 38-07473 Rev. *A Page 8 of 9 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY23020-3 Document History Page Document Title: CY23020-3 10-output, 400-MHz LVPECL Zero Delay Buffer Document Number: 38-07473 REV. ** *A ECN NO. 118965 126939 Issue Date 11/05/02 06/10/03 Orig. of Change HWT RGL New Data Sheet Fixed the block diagram (removed the C1 input) Description of Change Document #: 38-07473 Rev. *A Page 9 of 9 |
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